A clock generator often includes a phase-lock loop that generates an output clock signal based on reference clock signal. In operation, the phase-lock loop generates a feedback clock signal by dividing a frequency of the output clock signal and locks a phase and frequency of the feedback clock signal to a phase and frequency of the reference clock signal.
One characteristic of a phase-lock loop is an open-loop unity-gain. In conventional phase-lock loops, the open-loop unity-gain depends upon the reference clock signal and a divisor of a frequency divider. Additionally, the open-loop unity-gain of the phase-lock loop may depend upon variations in performance characteristics of components in the phase-lock loop. For example, an open-loop unity-gain of a phase-lock loop implemented in an integrated circuit may vary over process, voltage, and temperature variations in the integrated circuit. Because the open-loop unity-gain of the phase-lock loop depends upon the divisor of the frequency divider as well as variations in performance characteristics of component in the phase-lock loop, an open-loop unity-gain bandwidth of the phase-lock loop may not be within a specified frequency range. This can result in reduced production yield of the integrated circuit device and increased production cost of the integrated circuit device.
In light of the above, a need exists for a phase-lock loop having a controllable open-loop unity-gain. A further need exists for a phase-lock loop that compensates for process, voltage, and temperature variations in an integrated circuit including the phase-lock loop to maintain a substantially constant open-loop unity-gain of the phase-lock loop.